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C8051F380/1/2/3/4/5/6/7/C
SFR Definition 21.1. USB0XCN: USB0 Transceiver Control
Bit
7
6
5
4
3
2
1
0
Name
Type
PREN
R/W
PHYEN
R/W
SPEED
R/W
PHYTST[1:0]
R/W
DFREC
R
Dp
R
Dn
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD7; SFR Page = All Pages
Bit Name
Function
7
6
5
PREN
PHYEN
SPEED
Internal Pull-up Resistor Enable.
The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit.
0: Internal pull-up resistor disabled (device effectively detached from USB network).
1: Internal pull-up resistor enabled when VBUS is present (device attached to the
USB network).
Physical Layer Enable.
0: USB0 physical layer Transceiver disabled (suspend).
1: USB0 physical layer Transceiver enabled (normal).
USB0 Speed Select.
This bit selects the USB0 speed.
0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor
appears on the D– line.
1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor
appears on the D+ line.
4:3 PHYTST[1:0] Physical Layer Test Bits.
00: Mode 0: Normal (non-test mode) (D+ = X, D- = X)
01: Mode 1: Differential 1 Forced (D+ = 1, D- = 0)
10: Mode 2: Differential 0 Forced (D+ = 0, D- = 1)
11: Mode 3: Single-Ended 0 Forced (D+ = 0, D– = 0)
2
1
0
174
DFREC
Dp
Dn
Differential Receiver Bit
The state of this bit indicates the current differential value present on the D+ and D-
lines when PHYEN = 1.
0: Differential 0 signalling on the bus.
1: Differential 1 signalling on the bus.
D+ Signal Status.
This bit indicates the current logic level of the D+ pin.
0: D+ signal currently at logic 0.
1: D+ signal currently at logic 1.
D- Signal Status.
This bit indicates the current logic level of the D- pin.
0: D- signal currently at logic 0.
1: D- signal currently at logic 1.
Rev. 1.4
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